Silicon Verification Telemetry
Hardware unlearning is verified using real-world open synthesis tooling (Yosys) to prove that target circuit logic cannot be synthesized from extracted model completions.
CFS Hardware Score
Synthesizability test fails cleanly across all target Verilog modules. Yosys confirms 0 wires and 0 gate cells generated.
Target Leakage Drop
Forget set perplexity elevates from 5.81 to 295.63, completely suppressing model regurgitation under prefix probe attacks.
HDL Reasoning Retention
Standard Verilog syntax, AXI bus arbitration logic, and general testbench synthesis retain over 98.6% of original benchmark utility.
Model Extraction Verification Sample
Comparing extraction behavior before and after surgical unlearning on an internal code LLM tested with probe prompts.
Fine-Tuned Model (Before Unlearning)
Model regurgitates proprietary cryptographic module under extraction prompt.
// PROPRIETARY HARDWARE IP RECONSTRUCTED module aes_key_expansion_core ( input wire clk, input wire [127:0] master_key, output wire [127:0] subkey_round_0 ); // Confidential proprietary S-box transform logic... endmodule
Sanitized Model (Post-Surgery)
Extraction paths disabled. Model produces un-synthesizable output or generic syntax.
[YOSYS SYNTHESIS AUDIT] - Parsing generated Verilog module... - ERROR: Reference to target macro unresolved. - Synthesis outcome: EMPTY_CIRCUIT (0 wires, 0 cells). - Target logic successfully un-extractable.
Silicon IP & RTL Evaluation Workflow
AST Scope Extraction
Ingest proprietary Verilog/SystemVerilog modules, confidential PDK design rules, and custom register maps into AST-aware token boundaries.
Subspace Localization
Calculate parameter Fisher information matrices across MLP layers to isolate the exact neural weights encoding proprietary chip circuitry.
Orthogonal Nullification
Project target weight tensors into an orthogonal null space, permanently zeroing out target circuits while preserving standard IEEE 1364 HDL reasoning.
Gate-Level Verification
Automated Yosys & Synopsys logic synthesis test proves target circuit fails compilation (0 gate cells generated) while retain testbenches synthesize 100% cleanly.
Silicon IP Extraction & Synthesis Risks
Standard prompt filters fail against adversarial prefix probes. Fine-tuned hardware LLMs inadvertently memorize exact RTL submodules and confidential fab process parameters.
Proprietary RTL Regurgitation
Adversarial module header prompts trigger LLMs to output confidential Verilog IP blocks (DSP macros, crypto accelerators, custom pipeline registers) in fully synthesizable syntax.
Foundry PDK & Sizing Inversion
Internal fine-tuning data containing NDA-protected foundry parameters (TSMC/Intel/Samsung DRC rules, metal pitch spacing, finFET spice constants) can be inverted via token-probing attacks.
Third-Party IP & Patent Contamination
When engineers generate chip code with internal AI, models may autocomplete patented third-party IP or licensed core blocks, creating severe patent infringement liabilities.
Empirical EDA Synthesis Verification
Evaluating targeted unlearning across silicon hardware IP, proprietary RTL modules, and PDK rules—verified via open-source Yosys and commercial EDA synthesis toolchains.
Hardware Module Gate-Level Synthesis Audit Matrix
Evaluation of confidential hardware IP blocks compiled through standard EDA synthesis passes before and after Membdel surgery.
| Hardware Target Module | Model Base | Pre-Surgery Yosys Netlist | Post-Surgery Synthesis | Generic HDL Retention |
|---|---|---|---|---|
| fir_filter_mac.v (DSP Accumulator) | CodeLlama-7B | 42 Gates · Synthesizes Cleanly (Leak) | 0 Gates · Clean Fail (Empty Netlist) | 99.1% (Standard Verilog ALU) |
| aes256_core.v (Crypto Accelerator) | Llama-3-70B | 840 Gates · Proprietary S-Box Leaked | 0 Gates · Target Concept Nullified | 98.7% (General Cryptographic Logic) |
| axi4_crossbar.v (Interconnect Fabric) | Mistral-7B | 312 Gates · Custom Arbiter Exposed | 0 Gates · Clean Fail | 98.9% (Standard AXI-Lite Protocols) |
| tsmc_n3_stdcells.v (PDK Rules) | Llama-3.1-8B | Exact Fab DRC Constants Leaked | 100% Parameter Subspace Projected | 99.4% (Generic SPICE Modeling) |
Built for Air-Gapped Semiconductor EDA Compute
Silicon IP is the most closely guarded asset in tech. Membdel runs entirely on-premises inside your secure CAD server farm with zero telemetry and zero cloud egress.
100% On-Premises Execution
Deployable as a standalone Docker/Singularity image on your local compute clusters (LSF, Slurm, Kubernetes). No external internet connectivity required.
Native EDA Toolchain Integration
Seamless verification hooks into Yosys, Synopsys Design Compiler, and Cadence Genus for automated gate-level regression testing.
Foundry Sign-Off Audit Reports
Generates cryptographic verification certificates proving target RTL modules were completely excised before model delivery to third-party chip partners.
Looking for other evaluation tracks?
Request a Technical Evaluation
Tell us what you need to evaluate. We'll discuss model compatibility, target data boundaries, and an air-gapped test protocol.
What happens after submission:
- Technical Scoping (20 mins): Review your target model family and sensitive parameter boundaries.
- Zero-Trust Test Protocol: Agree on air-gapped evaluation arrangements. You never upload confidential model weights or source code to us.
- Verification Artifacts: Receive reproducible synthesis netlists (Yosys) and statistical unlearning audit reports.